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Principal/Sr. Staff SoC Design Verification Engineer

Company: Jobot
Location: Palo Alto
Posted on: May 15, 2022

Job Description:

Principal SoC Design Verification Engineer Needed / Bay Area / $200K This Jobot Job is hosted by Kevin Szilagyi Are you a fit? Easy Apply now by clicking the "Apply" button and sending us your resume. Salary $160,000 - $220,000 per year A Bit About Us If you are looking for a direct hire onsite opportunity this role is for you. Semiconductor start up company looking to bring on a Principal SoC Design Verification Engineer to their team. A rapidly growing ultralow-power wireless semiconductor startup with headquarters located in San Diego, CA with offices in the Bay area and Irvine. The start up is developing complete wireless solutions with significantly differentiated power dissipation/performance tradeoffs while innovative technology also dramatically improves wireless product flexibility and ease-of-use for product developers. We are looking for driven candidates to join our fast-paced and motivated team. This role is an excellent opportunity for someone that enjoys a small and agile group where you can make a great impact. We are developing complete wireless solutions with significantly differentiated power dissipation/performance tradeoffs. Our innovative technology also dramatically improves wireless product flexibility and ease-of-use for product developers. We are looking for driven candidates to join our fast-paced and motivated team to drive excellence in our 5G products. This role is an excellent opportunity for someone that enjoys driving the critical path and making a significant impact in launching products into the market and winning Why join us? Great compensation package Work with great technologies like IoT and 5G Room for growth Equity / Generous base salary of up to $200K for the right candidate Job Details Construct IP, SoC level test benches using verification components developed at the IP level. Test bench architecture for random/directed testing, stimulus generation, and checking to include custom and off the shelf VIP/UVCs. Develop and execute SoC verification plans focused on IP block interoperability and SOC/System level. Develop and execute verification plans based on design specifications and collaboration with architects and designers. Construct HW/SW Co-Verification Be part of a dynamic and functionally diverse team with opportunities for gaining exposure to modeling (TLM), HW emulation/acceleration, and SW driven verification. Utilize constrained random verification, functional coverage, code coverage and assertions to achieve goals. Job Requirements Master---s degree in engineering (or equivalent). 10 years of experience in design verification - Proven experience in full chip verification from test plan development to tape-out sign-off. Experience constructing chip-level System Verilog and UVM test bench environments, writing System Verilog Assertions (SVAs), with embedded software design and test. Experience executing block or chip-level verification plans. Experience with HW/SW Co-Verification - Developing test benches, test cases/use-cases, APIs, their execution, and debug. Excellent debug skills, with experience debugging RTL in block and/or chip-level environments. Extensive experience with a variety of verification tools and environments, and a deep understanding of their differences and capabilities to optimize the right methodology with schedules as the top priority. Experienced in SystemVerilog, UVM, and scripting languages like Python and Tcl. Expertise in using industry standard simulation tools such as NC Verilog, VCS, QuestaSim, etc. Excellent communication skills, energetic and self-motivated. Interested in hearing more? Easy Apply now by clicking the "Apply" button.

Keywords: Jobot, Palo Alto , Principal/Sr. Staff SoC Design Verification Engineer, Engineering , Palo Alto, California

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