Silicon Electrical Engineer - RTL Design
Location: Mountain View
Posted on: June 23, 2025
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Job Description:
Silicon Electrical Engineer - RTL Design 5 Job Summary: Talent
Software Services is in search of a Silicon Electrical Engineer -
RTL Design for a contract position in Mountain View, CA. The
opportunity will be three months with a strong chance for a
long-term extension. Primary Responsibilities/Accountabilities:
Create design specifications and test plans in collaboration with
other teams. Implement and verify RTL (Register Transfer Level)
designs for image and video processing blocks. Support verification
engineers to ensure bug-free silicon. Perform front-end synthesis
and analyze timing results. Run CDC and Lint for the design blocks.
Analyze and provide direction in terms of performance, gate count,
and power for various digital designs. Collaborate with
cross-functional teams to integrate IPs. Purpose of the Team: The
team focuses on silicon chip design for the latest cloud and AI
products. Key Projects: This role will support the design team with
design and flow work, writing scripts, and checking the quality of
CDC, RDC, and SoC integration work. Responsibilities include coding
in SystemVerilog and developing smaller IPs. This role may also
involve ad hoc tasks such as debugging and preventing failures.
Familiarity with subsystem view and AXI views is essential. Typical
Task Breakdown and Operating Rhythm: The majority of work involves
SoC integration, which will likely occupy 50% of the day. The
remaining time will be spent on additional projects that may take a
few weeks. Some weeks will involve supporting smaller IP
development projects, flow setup, and occasional case-by-case debug
work. Compelling Story & Candidate Value Proposition This role
provides the opportunity to work on top-of-the-line silicon chips
supporting the cloud. Qualifications: Years of Experience Required:
10 years of overall experience in the field. Degrees or
Certifications Required: A degree is not required, but a master's
degree is highly preferred. Best vs. Average: The ideal candidate
has familiarity with verification test benches, ARM core side
protocol, and significant experience with debugging. Previous
experience with tapeouts at large enterprise companies is also
preferred. Performance Indicators: Performance will be assessed
based on meeting the milestones assigned every two weeks. Minimum 5
years of experience with AXI protocol integration. Minimum 7 years
of experience contributing CDC and RDC work to successful SoC
tapeouts. Minimum 5 years of experience developing small IPs.
Preferred: Expertise in SystemVerilog and RTL design. Experience in
subsystem design and familiarity with AXI, APB protocols.
Experience in designing IPs and/or SoC integration. Strong
understanding of floating-point arithmetic implementation in RTL.
Substantial background in debugging designs and simulation
environments. Familiarity with design for test (DFT) and scan
concepts. Experience in scripting languages such as Python or Perl.
Proficiency in simulation, CDC, and lint checking tools. Bachelor's
degree in a related technical field required; a Master's degree is
preferred. 10 years of relevant experience in digital design and
successful tapeouts. If this job is a match for your background, we
would be honored to receive your application! Providing consulting
opportunities to TALENTed people since 1987, we offer a host of
opportunities, including contract, contract to hire and permanent
placement. Let's talk!
Keywords: , Palo Alto , Silicon Electrical Engineer - RTL Design, Engineering , Mountain View, California
